A master-slave arrangement is known from the Siemens catalogue ST 54.1, SIMATIC S5, Automatisierungsgerate, (Programmable Controllers), 1994 edition. In a mounting rail of a highly available programmable controller, a plurality of master units in the form of central processing units are linked via a backplane bus, designed in parallel, to a plurality of slave units designed as digital input/output modules, analog input/output modules, signal preprocessing modules or as communication modules.
The master units access the slave units in a reading or writing manner and different types of data, for example process, parameterization or diagnostic data, are exchanged between the master and slave units. To that end, the slave units usually have different memory regions in which the different types of data are stored and which the master units can access with appropriate addresses. To enable trouble-free access to this data, the master units must know both the size of the memory and its division into the different memory regions, as well as the type and arrangement of the different types of data within these regions. If, for example, a master unit tries to access diagnostic data of a slave unit which does not have any diagnostic functionality, and which is therefore not provided with any diagnostic data, then, in particular in programmable controllers, no disturbances should occur, for example, in the form of an extended bus usage. To avoid such disturbances, all of the slave units connected to the bus can be provided with memories of the same size, and the division of the regions, as well as the type and arrangement of the data, can be uniformly designed. However, this means that the respective memories of the slave units must be adapted both to the largest memory and to the largest memory region of the arrangement. As a result, a few slave memories are over-dimensioned and the size of the memory regions cannot be varied.
In German Patent Application No. P 44 40 789.0, an arrangement is suggested having at least one master unit linked via a bus to a plurality of slave units, each of which has a memory and which the master unit accesses in a reading and/or writing manner. Each slave unit has a protocol region, by way of which the master unit indicates to the slave unit an imminent memory access. The respective slave unit will grant or refuse access authorization to the master unit by way of this protocol region. The slave unit, in the case of access authorization, allocates to the master unit an address region of the memory, whose position the master unit reads out from the protocol region. The address region of the slave memory therefore depends on the bus address region.